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Freescale Semiconductor Advance Information
Document Number: MPC17517 Rev. 2.0, 7/2006
1.0 A 6.8 V Dual Motor Driver IC
The 17517 is a monolithic triple totem-pole-output power IC designed to be used in portable electronic applications to control small DC motors and solenoids. The 17517 can operate efficiently with supply voltages as low as 2.0 V to as high as 6.8 V. Its low RDS(ON) totem-pole output MOSFETs (0.46 typical) can provide continuous drive currents of 1.0 A and handle peak currents up to 3.0 A. It is easily interfaced to low-cost MCUs via parallel 3.0 V- or 5.0 V-compatible logic. The device can be pulse width modulated (PWM-ed) at up to 200 kHz. The 17517 can drive two motors in two directions one at a time or drive one motor in two directions and one solenoid with synchronous rectification of freewheeling currents one at a time. Two-motor operation is accomplished by hooking one motor between OUTA and OUTB and hooking the other motor between OUTB and OUTC. Motor plus solenoid operation is accomplished by hooking a motor between OUTA and OUTB and a solenoid between OUTC and GND. This device contains an integrated charge pump and level shifter (for gate drive voltages), integrated shoot-through current protection (cross-conduction suppression logic and timing), and undervoltage detection and shutdown circuitry. The 17517 has four operating modes: Forward, Reverse, Brake, and Tri-Stated (High Impedance). Features * 2.0 V to 6.8 V Continuous Operation * Output Current 1.0 A (DC), 3.0 A (Peak) * MOSFETs < 600 m RDS(ON) @ 25C Guaranteed * 3.0 V/ 5.0 V TTL- / CMOS-Compatible Inputs * PWM Frequencies up to 200 kHz * Undervoltage Shutdown
17517
DUAL MOTOR DRIVER
DTB SUFFIX 98ASH70247A 16-PIN TSSOP
ORDERING INFORMATION
Device MPC17517DTB/R2 Temperature Range (TA) -20C to 65C Package 16 TSSOP
5.0 V 17517 VDD C1L C1H C2L C2H Cres EN1 EN2 IN1 IN2
5.0 V VM OUTC
OUTA
Solenoid MOTOR
MCU
OUTB GND
Figure 1. 17517 Simplified Application Diagram
* This document contains certain information on a new product. Specifications and information herein are subject to change without notice.
(c) Freescale Semiconductor, Inc., 2006. All rights reserved.
INTERNAL BLOCK DIAGRAM
INTERNAL BLOCK DIAGRAM
C2L
OSC, Charge Pump
C2H
C1H Low Voltage Detector
C1L
VG
VMAB
VC
VMC
IN1
Level Shifter Predriver
OUTC
EN1
Control Logic
IN2
OUTB
OUTA
EN2
GND
Figure 2. 17517 Simplified Internal Block Diagram
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Analog Integrated Circuit Device Data Freescale Semiconductor
PIN CONNECTIONS
PIN CONNECTIONS
VDD VM OUTA CRES C2H C2L IN1 IN2
1 2 3 4 5 6 7 8
16 15 14 13 12 11 10 9
OUTC GND OUTB VM C1H C1L EN2 EN1
Figure 3. 17517 Pin Connections Table 1. 17517 Pin Definitions A functional description of each pin can be found in the Functional Pin Description section beginning on page 9.
Pin Number 1 2, 13 3 4 5 6 7 8 9 10 11 12 14 15 16 Pin Name VDD VM OUTA CRES C2H C2L IN1 IN2 EN1 EN2 C1L C1H OUTB GND OUTC Formal Name Control Circuit Power Supply Motor Drive Power Supply Output A Charge Pump Output Capacitor Connection Charge Pump 2H Charge Pump 2L Input Control 1 Input Control 2 Enable Control Signal Input 1 Enable Control Signal Input 2 Charge Pump 1L Charge Pump 1H Output B Ground Output C Definition Positive power source connection for control circuit. Motor power supply voltage input pins. Driver output A pin. Charge pump reservoir capacitor pin. Charge pump bucket capacitor 2 (positive pole). Charge pump bucket capacitor 2 (negative pole). Control signal input 1 pin. Control signal input 2 pin. Enable control signal input 1 pin. Enable control signal input 2 pin. Charge pump bucket capacitor 1 (negative pole). Charge pump bucket capacitor 1 (positive pole). Driver output B pin. Ground connection. Driver output C pin.
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ELECTRICAL CHARACTERISTICS MAXIMUM RATINGS
ELECTRICAL CHARACTERISTICS
MAXIMUM RATINGS
Table 2. Maximum Ratings All voltages are with respect to ground unless otherwise noted. Exceeding these ratings may cause a malfunction or permanent damage to the device.
Ratings ELECTRICAL RATINGS Motor Supply Voltage Charge Pump Output Voltage Logic Supply Voltage Signal Input Voltage Driver Output Current Continuous Peak (1) ESD Voltage
(2)
Symbol
Value
Unit
VM
-0.5 to 8.0 -0.5 to 14 -0.5 to 7.0 -0.5 to VDD + 0.5 1.0 3.0
V V V V A
V
CRES VDD VIN IO IOPK
V VESD1 VESD2 2000 100
Human Body Model Machine Model THERMAL RATINGS Storage Temperature Range Operating Junction Temperature Operating Ambient Temperature Thermal Resistance Power Dissipation
(3)
TSTG TJ TA RJA PD
-65 to 150 -20 to 150 -20 to 65 190 657 245
C C C C/W mW C
(4) (5)
Soldering Temperature
TSOLDER
Notes 1. TA = 25C, 10 ms pulse width at 200 ms intervals. 2. 3. 4. 5. ESD1 testing is performed in accordance with the Human Body Model (CZAP = 100 pF, RZAP = 1500 ), ESD2 testing is performed in accordance with the Machine Model (CZAP = 200 pF, RZAP = 0 ). 37 mm x 50 mm Cu area (1.6 mm FR-4 PCB). Maximum at TA = 25C. Soldering temperature limit is for 10 seconds maximum duration. Not designed for immersion soldering. Exceeding these limits may cause malfunction or permanent damage to the device.
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ELECTRICAL CHARACTERISTICS STATIC ELECTRICAL CHARACTERISTICS
STATIC ELECTRICAL CHARACTERISTICS
Table 3. Static Electrical Characteristics Characteristics noted under conditions TA = 25C, VDD = VM = 5.0 V, GND = 0 V unless otherwise noted. Typical values noted reflect the approximate parameter means at TA = 25C under nominal conditions unless otherwise noted.
Characteristic POWER Motor Supply Voltage Logic Supply Voltage Capacitor for Charge Pump Standby Power Supply Current Motor Supply Standby Current Logic Supply Standby Current Operating Power Supply Current Logic Supply Current
(7) (6)
Symbol
Min
Typ
Max
Unit
VM VDD C1, C2, C3 I I VMSTBY
2.0 2.7 0.01
5.0 5.0 0.1
6.8 5.7 1.0
V V F A mA mA
- -
- -
1.0 1.0
VDDSTBY I
Charge Pump Circuit Supply Current Low-Voltage Detection Circuit Detection Voltage (VDD)
(8)
IC
VDD
RES
- -
- -
3.0 0.7 V
VDDDET 1.5 RDS(ON) - 2.0 0.46 2.5 0.60
Driver Output ON Resistance (9) GATE DRIVE Gate Drive Voltage (10) No Current Load Gate Drive Ability (Internally Supplied) I CRES = -1.0 mA
V
W
VC RES
12 CRESLOAD 10 11.2 - 13 13.5
V
V
CONTROL LOGIC Logic Input Voltage Logic Input Function (2.7 V < VDD < 5.7 V) High-Level Input Voltage Low-Level Input Voltage High-Level Input Current Low-Level Input Current Notes 6. 7. 8. 9. 10. IV I
DDSTBY includes current to the predriver circuit.
VIN VIH VIL IIH IIL
0
-
VDD - VDD x 0.3 1.0 -
V
VDD x 0.7 - - -1.0
- - - -
V V A A
VDD includes current to the predriver circuit.
Detection voltage is defined as when the output becomes high-impedance after VDD drops below the detection threshold. When the gate V V voltage CRES is applied from an external source, CRES = 7.5 V. IO = 1.0 A source + sink. Input logic signal not present.
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ELECTRICAL CHARACTERISTICS DYNAMIC ELECTRICAL CHARACTERISTICS
DYNAMIC ELECTRICAL CHARACTERISTICS
Table 4. Dynamic Electrical Characteristics Characteristics noted under conditions TA = 25C, VDD = VM = 5.0 V, GND = 0 V unless otherwise noted. Typical values noted reflect the approximate parameter means at TA = 25C under nominal conditions unless otherwise noted.
Characteristic INPUT (IN1, IN2, EN1, EN2) Pulse Input Frequency Input Pulse Rise Time Input Pulse Fall Time OUTPUT Propagation Delay Time Turn-ON Time Turn-OFF Time Charge Pump Wake-Up Time (14) Low-Voltage Detection Time Notes 11. 12. 13. 14. tPLH tPHL tVGON tV DET
DD
(11)
Symbol
Min
Typ
Max
Unit
fIN tR tF
- - -
- - -
200 1.0 1.0
(12) (12)
kHz s s
(13)
s - - - - 0.1 0.1 0.1 - 0.5 0.5 3.0 10 ms ms
Time is defined between 10% and 90%. That is, the input waveform slope must be steeper than this. Time is defined between 90% and 10%. When C1 = C2 = C3 = 0.1 F.
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ELECTRICAL CHARACTERISTICS TIMING DIAGRAMS
TIMING DIAGRAMS
IN1, IN2, EN1, EN2
50% VDD 0.8 V/ 1.5 V
VDDDETon
2.5 V/3.5 V 50%
VDDDEToff
tPLH
OUTA, OUTB, OUTC 90%
tPHL
tV
DDDET
tV
90%
DDDET
10%
IM
0% (<1.0 A)
Figure 4. tPLH, tPHL, and tPZH Timing
Figure 5. Low-Voltage Detection Timing
VDD
t VGON
V
11 V
CRES
Figure 6. Charge Pump Timing
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ELECTRICAL CHARACTERISTICS TIMING DIAGRAMS
Table 5. Truth Table
INPUT IN1 IN2 EN1 EN2 OUTA OUTPUT OUTB OUTC
SHUTDOWN MODE X X L L Z Z Z
CHANNEL 1 (A-B) DRIVING MODE H H L L H L H L H H H H L L L L L H L Z L L H Z Z Z Z Z
CHANNEL 2 (B-C) DRIVING MODE H H L L H L H L L L L L H H H H Z Z Z Z L H L Z L L H Z
HALF-BRIDGE (C) DRIVING MODE H H L L H L H L H H H H H H H H Z Z Z Z Z Z Z Z Z H L Z
H = High. L = Low. Z = High impedance. X = Don't care.
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Analog Integrated Circuit Device Data Freescale Semiconductor
FUNCTIONAL DESCRIPTION INTRODUCTION
FUNCTIONAL DESCRIPTION
INTRODUCTION
The 17517 is a triple totem-pole output H-Bridge power IC designed to drive small dc motors used in portable electronics. The 17517 can operate efficiently with supply voltages as low as 2.0 V to as high as 6.8 V, and provide continuos motor drive currents of 1.0 A while handling peak currents up to 3.0 A. It is easily interfaced to low cost MCUs via parallel 3.0 V- or 5.0 V-compatible logic. The device can be pulse width modulated (PWM-ed) at up to 200 kHz. The 17517 can drive two motors in two directions one at a time; or it can drive one motor in two directions and one solenoid with synchronous rectification of freewheeling currents one at a time. Two-motor operation is accomplished by hooking one motor between OUTA and OUTB, and the other motor between OUTB and OUTC. Motor + solenoid operation is accomplished by hooking a motor between OUTA and OUTB and placing a solenoid between OUTC and GND. Table 5, Truth Table, page 8, describes the operating states versus the input conditions. As shown in Figure 2, 17517 Simplified Internal Block Diagram, page 2, the 17517 is a monolithic triple totem-pole output bridge with built-in charge pump circuitry. Each of the six MOSFETs forming the triple totem-pole output has an RDS(ON) of 0.6 (guaranteed by design). The IC has an integrated charge pump and level shifter (for gate drive voltages). Additionally, the IC has a built-in shoot-through current protection circuit and undervoltage lockout function. This IC has four operating modes: Forward, Reverse, Brake, and Tri-Stated (High Impedance).
FUNCTIONAL PIN DESCRIPTION DRIVER OUTPUT (OUTA, OUTB, OUTC)
These pins provide the connection to the internal power MOSFET triple-totem-pole H-bridge of the IC.
CONTROL SIGNAL INPUT AND ENABLE CONTROL SIGNAL INPUT (IN1, IN1, EN1, EN2)
These pins are input control pins used to control the outputs. These pins are 3.0 V/ 5.0 V CMOS-compatible inputs with hysteresis. These pins work together to control OUTA, OUTB, and OUTC (refer to Table 5, Truth Table).
GROUND (GND)
Power and signal ground pin.
CHARGE PUMP OUTPUT CAPACITOR (CRES)
This pin provides the connection for the external reservoir capacitor (output of the charge pump). Alternatively, this pin can also be used as an input to supply gate-drive voltage from an external source via a series current-limiting resistor. The voltage at the CRES pin will be approximately three times the VDD voltage, as the internal charge pump utilizes a voltage tripler circuit. The VDDRES voltage is used by the IC to supply gate drive for the internal power MOSFETs.
CHARGE PUMP BUCKET CAPACITOR (C1L, C1H, C2L, C2H)
These two pairs of pins, the C1L and C1H and the C2L and C2H, connect to the external bucket capacitors required by the internal charge pump. The typical value for the bucket capacitors is 0.1 F.
CONTROL CIRCUIT POWER SUPPLY (VDD)
This pin carries the logic supply voltage and current into the logic sections of the IC. VDD has an undervoltage threshold. If the supply voltage drops below the undervoltage threshold, the output power stage switches to a tri-state condition. When the supply voltage returns to a level that is above the threshold, the power stage automatically resumes normal operation according to the established condition of the input pins.
MOTOR DRIVE POWER SUPPLY (VM)
The two VM pins carry the main supply voltage and current into the power sections of the IC. This supply then becomes controlled and /or modulated by the IC as it delivers the power to the load attached between OUTA and OUTB. The VM pins must be connected together on the printed circuit board with as short as possible traces offering as low impedance as possible between pins.
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TYPICAL APPLICATIONS INTRODUCTION
TYPICAL APPLICATIONS
INTRODUCTION
Figure 7 shows a typical application for the 17517. When applying the gate voltage to the CRES pin from an external source, be sure to connect it via a resistor equal to, or greater than, RG = VCRES / 0.02 . 5.0 V 17517
VC
RES
< 14 V RG > VCRES /0.02 RG
NC NC NC NC
C1L C1H C2L C2H CRES
VDD
VM OUTA
0.01 F EN1
OUTB
MCU
EN2 IN1 IN1 GND OUTC
NC = No Connect
Figure 7. 17517 Typical Application Diagram
CEMF SNUBBING TECHNIQUES
Care must be taken to protect the IC from potentially damaging CEMF spikes induced when commutating currents in inductive loads. Typical practice is to provide snubbing of voltage transients by placing a capacitor or zener at the supply pin (VM) (see Figure 8).
PCB LAYOUT
When designing the printed circuit board (pcb), connect sufficient capacitance between power supply and ground pins to ensure proper filtering from transients. For all highcurrent paths, use wide copper traces and shortest possible distances.
5.0 V 5.0 V 17517 VDD VM C1L C1H C2L C2H CRES
OUT OUT
5.0 V 5.0 V 17517 VDD VM C1L C1H C2L C2H CRES
OUT OUT
GND
GND
Figure 8. CEMF Snubbing Techniques
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Analog Integrated Circuit Device Data Freescale Semiconductor
PACKAGING PACKAGE DIMENSIONS
PACKAGING
PACKAGE DIMENSIONS
For the most current package revision, visit www.freescale.com and perform a keyword search using the "98A" listed below.
DTB SUFFIX 16-PIN PLASTIC PACKAGE 98ASH70247A ISSUE B
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Analog Integrated Circuit Device Data Freescale Semiconductor
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PACKAGING PACKAGE DIMENSIONS
DTB SUFFIX 16-PIN PLASTIC PACKAGE 98ASH70247A ISSUE B
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Analog Integrated Circuit Device Data Freescale Semiconductor
REVISION HISTORY
REVISION HISTORY
REVISION 2.0
DATE 7/2006
DESCRIPTION OF CHANGES
* Implemented Revision History page * Converted to Freescale format and updated to the prevailing form and style
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MPC17517 Rev. 2.0 7/2006

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